#52 Implement and test the following combinational
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- The inputs (A, B) are 4-bits
- The output also is 4-bits
- The circuit will operate the output of the circa the circuit is) as following.
Procedure
- Implement the 1-bit binary adder/subtractor using structural Verilog HDL code.
- Use the created module of 1-bit binary adder/subtractor to build 4-bit adder/subtractor structurally, then using Quartus to create a symbol for it.
- Write the module of 1-digit BCD adder/subtractor, then using Quartus to create a symbol for it
- Write the code of MAX module, then using Quartus to create a symbol for it.
- Write the code of the MIN module, then using Quartus to create a symbol for it.
Procedure
- Implement the 1-bit binary adder/subtractor using structural Verilog HDL code.
- Use the created module of 1-bit binary adder/subtractor to build 4-bit adder/subtractor structurally, then using Quartus to create a symbol for it
- Write the module of 1-digit BCD adder/subtractor, then using Quartus to create a symbol for it
- Write the code of MAX module, then using Quartus to create a symbol for it.
- Write the code of the MIN module, then using Quartus to create a symbol for it.
- Write a Verilog HDL code to describe the module 4-bit 4x1 multiplexer, then using Quartus to create a symbol for it
- Test each module
- Use Quartus schematic to describe the whole system from its subsystems.
- Test the whole system
Project Report
The report document must contain sections highlighting the following
1 - Design and implementation
- Specity clearly the design and implementation details of each components
- Provide drawings of the component circuits and the overall system
- Carry out the design and implementation with the following aspects in mind:
i Correctness of the individual components
ii Correctness of the overall design when wiring the components together
iii Completeness: all operation were implemented properly.
2 - Simulation and Testing
- Carry out the simulation of each component.
- Carry out the simulation of the whole system
- Also provide snapshots of the Simulator window with your test cases and showing the simulation output results.
3- Teamwork
- Two students can form a group
- Group members are required to coordinate the work equally among themselves so that everyone is involved in all the following activities
i Design and implementation
ii Simulation and Testing .
- Clearly show the work done by each group member
Submission Guidelines
Attach one zip file containing all the design circuits, the pr programs source code Screenshot is not allowed in writing the code (copy the code from Quartus software) as well as the report document to Raj as a reply to this message.
Grading policy
The grade will be divided according to the following components:
1. Correctness: whether your implementation is working
2. Completeness and testing whether all components and cases have been implemented, handled, and tested properly
3. Participation and contribution to the project
4. Report document
module adder_subtractor(S, C, V, A, B, Op);
output [3:0] S;
output C,V;
input [3:0] A,B;
input Op; // The operation: 0 => Add, 1=>Subtract.
wire C0, C1, C2, C3;
wire B0, B1, B2, B3;
xor(B0, B[0], Op);
xor(B1, B[1], Op);
xor(B2, B[2], Op);
xor(B3, B[3], Op);
xor(C, C3, Op);
xor(V, C3, C2);
full_adder fa0(S[0], C0, A[0], B0, Op);
full_adder fa1(S[1], C1, A[1], B1, C0);
full_adder fa2(S[2], C2, A[2], B2, C1);
full_adder fa3(S[3], C3, A[3], B3, C2);
endmodule
module full_adder(S, Cout, A, B, Cin);
output S, Cout;
input A,B, Cin;
wire w1,w2,w3,w4;
xor(w1, A, B);
xor(S, Cin, w1);
and(w2, A, B);
and(w3, A, Cin);
and(w4, B, Cin);
or(Cout, w2, w3, w4);
endmodule
module max(input [3:0]A, input [3:0]B, output [3:0]out3);
reg [3:0]max;
always @(*)
begin
if((A)>B)
max=A;
else
max=B;
end
assign out3=max;`
endmodule
module min(input [3:0]A, input [3:0]B, output [3:0]out4);
reg [3:0]min;
always @(*)
begin
if((A)>B)
min=B;
else
min=A;
end
assign out4=min;`
endmodule
module mux4_1( a, b, c, d, s0, s1, out);
input wire a, b, c, d;
input wire s0, s1;
output reg out;
always @ (a or b or c or d or s0, s1)
begin
case (s0 | s1)
2'b00 : out <= a;
2'b01 : out <= b;
2'b10 : out <= c;
2'b11 : out <= d;
endcase
end
endmodule
module bcd(a,b,carry_in,sum,carry,op);
input [3:0] a,b;
input carry_in,op;
output [3:0] sum;
output carry;
reg [4:0] sum_temp;
reg [3:0] sum;
reg carry;
always @(a,b,carry_in,op)
begin
sum_temp = a+b+carry_in;
if(sum_temp > 9)
begin
sum_temp = sum_temp+6;
carry = 1;
sum = sum_temp[3:0];
end
else
begin
carry = 0;
sum = sum_temp[3:0];
end
end
endmodule
ChemistryExplain team has covered all Topics related to inorganic, organic, physical chemistry, and others So, Prepare these Chemistry Questions and Answers with Explanation Pdf.
Question
#52 Implement and test the following combinational circuit using Verilog HDL.
Notes:
- The inputs (A, B) are 4-bits
- The output also is 4-bits
- The circuit will operate the output of the circa the circuit is) as following.
- Implement the 1-bit binary adder/subtractor using structural Verilog HDL code.
- Use the created module of 1-bit binary adder/subtractor to build 4-bit adder/subtractor structurally, then using Quartus to create a symbol for it.
- Write the module of 1-digit BCD adder/subtractor, then using Quartus to create a symbol for it
- Write the code of MAX module, then using Quartus to create a symbol for it.
- Write the code of the MIN module, then using Quartus to create a symbol for it.
- Implement the 1-bit binary adder/subtractor using structural Verilog HDL code.
- Use the created module of 1-bit binary adder/subtractor to build 4-bit adder/subtractor structurally, then using Quartus to create a symbol for it
- Write the module of 1-digit BCD adder/subtractor, then using Quartus to create a symbol for it
- Write the code of MAX module, then using Quartus to create a symbol for it.
- Write the code of the MIN module, then using Quartus to create a symbol for it.
- Write a Verilog HDL code to describe the module 4-bit 4x1 multiplexer, then using Quartus to create a symbol for it
- Test each module
- Use Quartus schematic to describe the whole system from its subsystems.
- Test the whole system
Project Report
The report document must contain sections highlighting the following
1 - Design and implementation
- Specity clearly the design and implementation details of each components
- Provide drawings of the component circuits and the overall system
- Carry out the design and implementation with the following aspects in mind:
i Correctness of the individual components
ii Correctness of the overall design when wiring the components together
iii Completeness: all operation were implemented properly.
2 - Simulation and Testing
- Carry out the simulation of each component.
- Carry out the simulation of the whole system
- Also provide snapshots of the Simulator window with your test cases and showing the simulation output results.
3- Teamwork
- Two students can form a group
- Group members are required to coordinate the work equally among themselves so that everyone is involved in all the following activities
i Design and implementation
ii Simulation and Testing .
- Clearly show the work done by each group member
Submission Guidelines
Attach one zip file containing all the design circuits, the pr programs source code Screenshot is not allowed in writing the code (copy the code from Quartus software) as well as the report document to Raj as a reply to this message.
Grading policy
The grade will be divided according to the following components:
1. Correctness: whether your implementation is working
2. Completeness and testing whether all components and cases have been implemented, handled, and tested properly
3. Participation and contribution to the project
4. Report document
Answer
module adder_subtractor(S, C, V, A, B, Op);
output [3:0] S;
output C,V;
input [3:0] A,B;
input Op; // The operation: 0 => Add, 1=>Subtract.
wire C0, C1, C2, C3;
wire B0, B1, B2, B3;
xor(B0, B[0], Op);
xor(B1, B[1], Op);
xor(B2, B[2], Op);
xor(B3, B[3], Op);
xor(C, C3, Op);
xor(V, C3, C2);
full_adder fa0(S[0], C0, A[0], B0, Op);
full_adder fa1(S[1], C1, A[1], B1, C0);
full_adder fa2(S[2], C2, A[2], B2, C1);
full_adder fa3(S[3], C3, A[3], B3, C2);
endmodule
module full_adder(S, Cout, A, B, Cin);
output S, Cout;
input A,B, Cin;
wire w1,w2,w3,w4;
xor(w1, A, B);
xor(S, Cin, w1);
and(w2, A, B);
and(w3, A, Cin);
and(w4, B, Cin);
or(Cout, w2, w3, w4);
endmodule
module max(input [3:0]A, input [3:0]B, output [3:0]out3);
reg [3:0]max;
always @(*)
begin
if((A)>B)
max=A;
else
max=B;
end
assign out3=max;`
endmodule
module min(input [3:0]A, input [3:0]B, output [3:0]out4);
reg [3:0]min;
always @(*)
begin
if((A)>B)
min=B;
else
min=A;
end
assign out4=min;`
endmodule
module mux4_1( a, b, c, d, s0, s1, out);
input wire a, b, c, d;
input wire s0, s1;
output reg out;
always @ (a or b or c or d or s0, s1)
begin
case (s0 | s1)
2'b00 : out <= a;
2'b01 : out <= b;
2'b10 : out <= c;
2'b11 : out <= d;
endcase
end
endmodule
module bcd(a,b,carry_in,sum,carry,op);
input [3:0] a,b;
input carry_in,op;
output [3:0] sum;
output carry;
reg [4:0] sum_temp;
reg [3:0] sum;
reg carry;
always @(a,b,carry_in,op)
begin
sum_temp = a+b+carry_in;
if(sum_temp > 9)
begin
sum_temp = sum_temp+6;
carry = 1;
sum = sum_temp[3:0];
end
else
begin
carry = 0;
sum = sum_temp[3:0];
end
end
endmodule
Labels: Q&A Other
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