#492 Design a 16-1 MUX using any number of lower

Design a 16-1 MUX using any number of lower - Computer Science

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Question 2. Design a 16-1 MUX using any number of lower MUXs, such as 8-1 or 4-1 only. No other gates are allowed.

Question 3. In the following circuit, all gates, including the inverter, have an inertial delay of 8 ns except for gate 3, which has a 30 ns delay.

A. Write a VHDL code that gives a dataflow description of the circuit. All delays should be inertial delays.

B. Using any VHDL simulator, simulate the circuit. (Use a View Interval of 200 ns.) Initially set A = 1, B = 1, C = 1 and D = 0, then run the simulator for 60 ns. Change B to 0, and run the simulator for 60 ns. Record the waveform.

C. Change the VHDL code of Part (A) so that the inverter has a 5 ns delay.

D. Repeat Part (B).

E. Change the VHDL code of Part (c) so that gates 4 and 5 have a transport delay rather than an inertial delay.

F. Repeat Part (B)

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